Sfoglia per Autore PACINI, TOMMASO
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MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs
2020-01-01 Dinelli, G.; Meoni, G.; Rapuano, E.; Pacini, T.; Fanucci, L.
An FPGA-based hardware accelerator for CNNs inference on board satellites: Benchmarking with Myriad 2-based solution for the cloudscout case study
2021-01-01 Rapuano, E.; Meoni, G.; Pacini, T.; Dinelli, G.; Furano, G.; Giuffrida, G.; Fanucci, L.
A multi-cache system for on-chip memory optimization in fpga-based cnn accelerators
2021-01-01 Pacini, T.; Rapuano, E.; Dinelli, G.; Fanucci, L.
A Post-training Quantization Method for the Design of Fixed-Point-Based FPGA/ASIC Hardware Accelerators for LSTM/GRU Algorithms
2022-01-01 Rapuano, Emilio; Pacini, Tommaso; Fanucci, Luca
Design and Implementation of an FPGA-Based CNN Hardware Accelerator Using Partial Reconfigurability: The CloudScout Case Study
2022-01-01 Comino, C.; Pacini, T.; Rapuano, E.; Fanucci, L.
Towards the Extension of FPG-AI Toolflow to RNN Deployment on FPGAs for On-board Satellite Applications
2023-01-01 Pacini, T.; Rapuano, E.; Tuttobene, L.; Nannipieri, P.; Fanucci, L.; Moranti, S.
FPG-AI: A Technology-Independent Framework for the Automation of CNN Deployment on FPGAs
2023-01-01 Pacini, T; Rapuano, E; Fanucci, L
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