Sfoglia per Autore  

Opzioni
Mostra risultati da 1 a 20 di 240
Titolo Data di pubblicazione Autore(i) File
An Algorithm for Asynchronous NMOS CMOS Network Analysis in a CAD Tool for Physical Fault Simulation 1-gen-1984 Melgara, M.; Paolini, M.; Roncella, Roberto
Automatic Faults Generator at Register Transfer (RT)-Level 1-gen-1984 Melgara, M.; Paolini, M.; Roncella, Roberto; Morpurgo, S.
A Single Chip Adaptive Filter for Delta-Modulated Signals 1-gen-1987 Terreni, Pierangelo; Roncella, Roberto; Saletti, Roberto
VLSI systolic filter with ternary coefficients for delta-modulated signals 1-gen-1988 Terreni, Pierangelo; Roncella, Roberto; Picchi, G.; Saletti, Roberto
A VLSI Systolic Filter with ternary coefficients for Delta-Modulated Signals 1-gen-1988 Terreni, Pierangelo; Roncella, Roberto; Picchi, G.; Saletti, Roberto
A VLSI Systolic Adder for Digital Filtering of Delta-Modulated Signals 1-gen-1989 Roncella, Roberto; Saletti, Roberto
An application of a systolic macrocell based VLSI design style: a single-chip high-performance FIR filter 1-gen-1989 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo; Piatelli, D.
An Example of a New VLSI Design Style Based on Systolic Macrocells - A High-Speed Single-Chip Transversal Filter for Signal-Processing Applications 1-gen-1990 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo
Dedicated systolic VLSI circuit as adaptive filter for acoustic echo canceller 1-gen-1991 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo
Single-Chip Systolic FIR Filter for Acoustic Echo Cancellation 1-gen-1991 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo; Toncelli, C.
Dedicated Systolic VLSI Circuit as Adaptive Filter for Acoustic Echo Canceller 1-gen-1991 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo
A Novel Bit-Level Systolic Array Median Filter 1-gen-1991 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo
Sistema di accensione a microonde a scarica libera 1-gen-1991 Gentili, Roberto; Roncella, Roberto; STARA GIOVANNI, Vincenzo; Terreni, Pierangelo
Application of a Systolic Macrocell-Based VLSI Design Style to the Design of a Single-Chip High-Performance FIR Filter 1-gen-1991 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo; Piatelli, D.
Full-Custom Design of Integrated Circuits as Dissertation Exercise for EE Students at the University of Pisa 1-gen-1991 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo
ASIC-BASED ACOUSTIC ECHO-CANCELER BOARD FOR VME BUS 1-gen-1992 Maloberti, F.; Torelli, G.; Panini, C.; Troiani, M.; Roncella, Roberto; Terreni, Pierangelo; Toncelli, C.; Saletti, Roberto
Single-Chip Adaptive FIR Filter for Acoustic Echo Canceler Board 1-gen-1992 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo; Toncelli, C.
A DCT systolic chip for digital HDTV 1-gen-1992 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo
Design of a High-Speed Custom VLSI Signal Interpolator Chip 1-gen-1992 Luise, Marco; Roncella, Roberto
70-MHz 2-μm CMOS Bit-level Systolic Arrat Median Filter 1-gen-1993 Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo
Mostra risultati da 1 a 20 di 240
Legenda icone

  •  file ad accesso aperto
  •  file disponibili sulla rete interna
  •  file disponibili agli utenti autorizzati
  •  file disponibili solo agli amministratori
  •  file sotto embargo
  •  nessun file disponibile