This chapter addresses the problem of functional verification of IP cores to be integrated in complex embedded systems. After analyzing the limits of methods based on HDL testbenches or formal verification, a pseudorandom coverage-driven approach is presented (verification environment design guidelines together with a final coverage report summary) and applied to a novel Router IP core design, a key component of Networkon- Chip communication infrastructure in embedded systems
Coverage-driven Verification of HDL IP cores
SAPONARA, SERGIO;PETRI, ESA;FANUCCI, LUCA;
2011-01-01
Abstract
This chapter addresses the problem of functional verification of IP cores to be integrated in complex embedded systems. After analyzing the limits of methods based on HDL testbenches or formal verification, a pseudorandom coverage-driven approach is presented (verification environment design guidelines together with a final coverage report summary) and applied to a novel Router IP core design, a key component of Networkon- Chip communication infrastructure in embedded systemsFile in questo prodotto:
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