The paper deals with the application of a VLSI design style based on systolic macrocells in the realisation of a single-chip high-performance digital FIR filter. The systolic macrocell design style is well suited for the design of high-performance integrated circuits to be used in digital signal processing. The style uses as design primitives bit-level systolic macrocells designed according to logical and electrical rules that guarantee the required performance. The filter was designed with a 1.5-mu-m CMOS technology; it occupies an area of 3.74 x 3.42 mm2 and has 128 coefficients. The expected clock frequency is of about 100 MHz and allows a throughput of the order of 1 million samples per second. The technique applied to the design of the most critical part of the circuit (the clock generation and distribution network) is also described.
Application of a Systolic Macrocell-Based VLSI Design Style to the Design of a Single-Chip High-Performance FIR Filter
RONCELLA, ROBERTO;SALETTI, ROBERTO;TERRENI, PIERANGELO;
1991-01-01
Abstract
The paper deals with the application of a VLSI design style based on systolic macrocells in the realisation of a single-chip high-performance digital FIR filter. The systolic macrocell design style is well suited for the design of high-performance integrated circuits to be used in digital signal processing. The style uses as design primitives bit-level systolic macrocells designed according to logical and electrical rules that guarantee the required performance. The filter was designed with a 1.5-mu-m CMOS technology; it occupies an area of 3.74 x 3.42 mm2 and has 128 coefficients. The expected clock frequency is of about 100 MHz and allows a throughput of the order of 1 million samples per second. The technique applied to the design of the most critical part of the circuit (the clock generation and distribution network) is also described.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
