In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware-software (HW-SW) partitioning assuming power consumption. flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW-SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform. (C) 2002 Elsevier Science Ltd. All rights reserved.

VLSI architecture for a low-power video codec system

FANUCCI, LUCA;SAPONARA, SERGIO
2002-01-01

Abstract

In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware-software (HW-SW) partitioning assuming power consumption. flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW-SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform. (C) 2002 Elsevier Science Ltd. All rights reserved.
2002
Chimienti, A; Fanucci, Luca; Locatelli, R; Saponara, Sergio
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/178654
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