Automated Design of FFT/IFFT Processors for Advanced Telecom Applications

The paper presents an automated environment for the generation of high performance Fast Fourier Transform (FFT/IFFT) macrocells. It is based on circuit-level VHDL and system-level C++ models of a parametric cascade architecture supporting different types of arithmetic. Moreover it is able to generate various test signals and to carry out a rapid processor accuracy analysis changing both architecture parameters and type of arithmetic. After high-level analysis a VHDL database is generated ready for logic synthesis and gate-level design and test. As case studies, the generation of FFT/IFFT cells for multi carrier wireless (UWB) and wireline (xDSL) communication is presented.