Recent Development on Triple Well 130 nm CMOS MAPS with in-Pixel Signal Processing and Data Sparsification Capability

A different approach to the design of CMOS MAPS has recently been proposed. By exploiting the triple well option of a CMOS commercial process, a deep n-well (DNW) MAPS sensor has been realized with a full in-pixel signal processing chain: charge preamplifier, shaper, discriminator and a latch. This readout approach beeing compatible with data sparsification will improve the readout speed potential of MAPS sensors. The first protoype chips, realized with STMicroelectronics 130 nm triple well process, proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from 55Fe and electrons from 90Sr. Extensive tests performed to characterize the second generation of the APSEL chips based on the DNW MAPS design are reported. Small 3times3 pixel matrices with full analog output have been tested with radioactive sources to characterize charge collection. Pixel noise equivalent charge (ENC) of 50 e- and signal-to-noise ratio for MIPs of about 14 have been measured. Improved pixel noise and reduced threshold dispersion (about 100 e-) have been measured in the 8times8 matrix with a sequential readout. Based on the new DNW MAPS design a dedicated fast readout architecture to perform on-chip data sparsification is currently under development. The aim is to incorporate in the same detector the advantages of the thin CMOS sensors and similar functionalities as in hybrid pixels.