Intellectual Property Macrocell for SpaceWire Interface Compliant with AMBA-APB Bus

Modern satellite systems require the transfer of huge amount of data on board to the satellite. This is particularly critical for future, high-capability remote-sensing missions. To address this issue, the European Space Agency proposed a new serial data link standard, named SpaceWire (ECSS-E-50-12A). In order to simplify the development of complex System On Chip (SoC) featuring a SpaceWire interface for external communications it is of paramount importance the availability of a SpaceWire Interface Intellectual Property (IP) macrocell compliant with a system bus and developed according to a proper design and verification methodology. In this paper we present the VLSI design of a SpaceWire interface for the AMBA APB bus, compliant with the SpaceWire standard and the AMBA 2.0 specifications. Particular attention has been devoted to the verification methodology in order to increase the reliability of the IP macrocell. The SpaceWire interface for APB bus is composed by a SpaceWire Encoder-Decoder without buffers and a wrapper for a 32 bits APB bus containing the registers necessary to control the interface, the buffers and the logic to exploit the 32 bits width of the APB bus by transferring two 9 bits tokens in a single bus cycle. The proposed verification methodology used in the development of the SpaceWire interface consists of 4 verification steps: block level, bus level, system level and prototype level. The block-level simulation aims to verify the IP functionality when it is considered as stand alone. The checks are related to the reset condition, to the register read/write accesses and to the IP behaviour during exploitation of its functionality. The bus-level simulation phase aims to guarantee the absence of conflicts between the IP and other peripherals. The checks are mainly related to the register read/write accesses. The system-level simulation phase aims to verify the correct IP functionality once it is plugged on the whole SoC. The main difference with respect to the previous phases is that in this environment the processor is used to perform all operations needed to verify the IP. Since we are currently applying this verification methodology also to the LEON platform, we have tested the SpaceWire IP within the same environment. Particularly, data transfer between two SpaceWire interfaces connected together have been verified by using the LEON CPU running a proper software routine. The last step consists on prototype level verification, in which the whole system is synthesized and fitted on an FPGA board. To verify the system behaviour the same routines developed for the System level are run and relevant results compared with the System level ones. The SpaceWire Interface design has been developed according to a design for reuse approach, based on VHDL which lead to a parametric (number of characters in the FIFO) and technology-independent description refined up to a register transfer level (RTL). The circuit has been characterized by means of logic synthesis for a 0.18 um CMOS standard-cell technology resulting in an overall 3.5 Kgates complexity (buffers excluded) and a maximum data rate of 100 Mbps.