This work presents the design of a read-out channel suitable for application to silicon pixel detectors for the next generation Free Electron Laser (FEL) experiments. The readout architecture, which has been carried out in a 65 nm CMOS technology, consists of a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaping stage and a low-power analog-to-digital converter (ADC), hosted in a 100 μm-pitch pixel. The blocks will be operated in such a way to cope with the high frame rates (exceeding 1 MHz) foreseen for future X-ray FEL machines. The paper describes in detail the architecture and the performance of the CSA and provides an overview about the analog readout channel.
Low-noise readout channel with a novel dynamic signal compression for future X-FEL applications
BATIGNANI, GIOVANNI;BETTARINI, STEFANO;CASAROSA, GIULIA;FORTI, FRANCESCO;MORSANI, FABIO;PALADINO, ANTONIO;PAOLONI, EUGENIO;RIZZO, GIULIANA;
2014-01-01
Abstract
This work presents the design of a read-out channel suitable for application to silicon pixel detectors for the next generation Free Electron Laser (FEL) experiments. The readout architecture, which has been carried out in a 65 nm CMOS technology, consists of a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaping stage and a low-power analog-to-digital converter (ADC), hosted in a 100 μm-pitch pixel. The blocks will be operated in such a way to cope with the high frame rates (exceeding 1 MHz) foreseen for future X-ray FEL machines. The paper describes in detail the architecture and the performance of the CSA and provides an overview about the analog readout channel.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
