This paper addresses the problem of power optimization of Intellectual Property (IP) digital macrocells in embedded control systems. With reference to the case study of an 8051-compliant microcontroller, first the IP cell is analyzed to highlight the main building blocks contributing to power consumption; then Register Transfer Level (RTL) techniques such as state encoding, clock gating and operand isolation are applied to reduce dynamic power consumption. As final result, when implementing the original and the modified IP in submicron CMOS standard-cells technology, a considerable decrease of power consumption, up to 40%, is achieved at the expenses of limited area and timing overheads. Our custom clock gating is also compared to the automatic clock gating insertion performed by commercial CAD tools, proving its higher power optimization efficiency. The proposed approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the VHDL source code. Being technology and CAD independent, these architecture-level optimizations can be combined with other low-power techniques proposed in literature at different design levels.
POWER OPTIMIZATION OF DIGITAL IP MACROCELLS FOR EMBEDDED CONTROL SYSTEMS
SAPONARA, SERGIO;FANUCCI, LUCA;
2004-01-01
Abstract
This paper addresses the problem of power optimization of Intellectual Property (IP) digital macrocells in embedded control systems. With reference to the case study of an 8051-compliant microcontroller, first the IP cell is analyzed to highlight the main building blocks contributing to power consumption; then Register Transfer Level (RTL) techniques such as state encoding, clock gating and operand isolation are applied to reduce dynamic power consumption. As final result, when implementing the original and the modified IP in submicron CMOS standard-cells technology, a considerable decrease of power consumption, up to 40%, is achieved at the expenses of limited area and timing overheads. Our custom clock gating is also compared to the automatic clock gating insertion performed by commercial CAD tools, proving its higher power optimization efficiency. The proposed approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the VHDL source code. Being technology and CAD independent, these architecture-level optimizations can be combined with other low-power techniques proposed in literature at different design levels.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
