As an enhancement of the state-of-the-art solutions, a high-throughput architecture of a decoder for structured LDPC codes is presented in this paper. Thanks to the peculiar code definition and to the envisaged architecture featuring memory paging, the decoder is very flexible, and the support of different code rates is achieved with no significant hardware overhead. A top-down design flow of a real decoder is reported, starting from the analysis of the system performance in finite-precision arithmetic, up to the VLSI implementation details of the elementary modules. The synthesis of the whole decoderon 0.18 mu m standard cells CMOS technology showed remarkable performances: small implementation loss (0.2 dB down to BER = 10(-8)), low latency (less than 6.0 mu s), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).
High-throughput multi-rate decoding of structured Low-Density Parity-Check codes
FANUCCI, LUCA;
2005-01-01
Abstract
As an enhancement of the state-of-the-art solutions, a high-throughput architecture of a decoder for structured LDPC codes is presented in this paper. Thanks to the peculiar code definition and to the envisaged architecture featuring memory paging, the decoder is very flexible, and the support of different code rates is achieved with no significant hardware overhead. A top-down design flow of a real decoder is reported, starting from the analysis of the system performance in finite-precision arithmetic, up to the VLSI implementation details of the elementary modules. The synthesis of the whole decoderon 0.18 mu m standard cells CMOS technology showed remarkable performances: small implementation loss (0.2 dB down to BER = 10(-8)), low latency (less than 6.0 mu s), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
