CINECA IRIS Institutional Research Information System

ALIA, GIUSEPPE Statistiche

ALIA, GIUSEPPE  

DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE  

Mostra records
Risultati 1 - 20 di 30 (tempo di esecuzione: 0.026 secondi).
Titolo Data di pubblicazione Autore(i) File
A fast near optimum VLSI implementation of FFT using residue number systems 1-gen-1984 Alia, Giuseppe; Barsi, F; Martinelli, E.
A fast RNS digital neural processor 1-gen-1999 Alia, Giuseppe; Martinelli, E.
A fast VLSI conversion between binary and residue systems 1-gen-1984 Alia, Giuseppe; Barsi, F; Martinelli, E.
A high performance ROM-based structure for modular exponentiation 1-gen-2011 Alia, Giuseppe; Martinelli, E.
A procedure to determine optimal partition of weighted hypergraphs through a network flow analogy 1-gen-1976 Alia, Giuseppe; Maestrini, P.
A VLSI algorithm for direct and reverse conversion from Weighted Binary Number System to Residue Number System 1-gen-1984 Alia, Giuseppe; Martinelli, E.
A VLSI modulo m multiplier 1-gen-1991 Alia, Giuseppe; Martinelli, E.
A VLSI structure for X(mod m) operation 1-gen-1990 Alia, Giuseppe; Martinelli, E.
Addition and overflow handling in a class of redundant RNS with magnitude index 1-gen-1987 Alia, Giuseppe; Barsi, F; Martinelli, E.
Analisi temporale in un simulatore funzionale 1-gen-1977 Alia, Giuseppe; Bernardini, F; Ciompi, P; Martinelli, E.
Angular spline: a new approach to the interpolation problem in computer graphics 1-gen-1987 Alia, Giuseppe; Barsi, F; Martinelli, E; Tani, N.
Automed module placement and wire routeing according to a structured biplanar scheme in printed boards 1-gen-1973 Alia, Giuseppe; Frosini, G; Maestrini, P.
Designing multioperand modular adders 1-gen-1996 Alia, Giuseppe; Martinelli, E.
Fast hardware graphic generators of curve families 1-gen-1986 Alia, Giuseppe; Martinelli, E; Tani, N.
Fast modular exponentiation of large numbers with large exponents 1-gen-2002 Alia, Giuseppe; Martinelli, E.
Logic design of a fast circuit for iterative additions in Redundant Hybrid Number Systems 1-gen-1998 Alia, Giuseppe; Martinelli, E.
Modellamento dei guasti in un simulatore funzionale 1-gen-1977 Alia, Giuseppe; Bernardini, F; Ciompi, P; Martinelli, E; Simoncini, L.
NEUROM: a ROM based RNS digital neuron 1-gen-2005 Alia, Giuseppe; Martinelli, E.
On switching network functionalities and their relationships 1-gen-1982 Alia, Giuseppe; Martinelli, E.
On the lower bound to the VLSI complexity of Number conversion from Weighted to Residue representation 1-gen-1993 Alia, Giuseppe; Martinelli, E.