This paper presents a simplified, low-complexity check node processor for a decoder of LDPC codes. This is conceived as the combination of the modified Min-Sum decoding with the reduction of the number of computed messages to only P+1 different values. The simulations with a random code used as a case study show that this technique performs excellently even when only two different values are propagated (P = 1). This result is assumed as the basement to the design of an optimised serial architecture. The logic synthesis on 0.18 μm CMOS technology shows that our design outperforms in complexity similar state-of-the-art solutions and makes the check node operations no longer critical to the complexity of the whole decoder.
High-Precision LDPC Codes Decoding at the Lowest Complexity
FANUCCI, LUCA
2006-01-01
Abstract
This paper presents a simplified, low-complexity check node processor for a decoder of LDPC codes. This is conceived as the combination of the modified Min-Sum decoding with the reduction of the number of computed messages to only P+1 different values. The simulations with a random code used as a case study show that this technique performs excellently even when only two different values are propagated (P = 1). This result is assumed as the basement to the design of an optimised serial architecture. The logic synthesis on 0.18 μm CMOS technology shows that our design outperforms in complexity similar state-of-the-art solutions and makes the check node operations no longer critical to the complexity of the whole decoder.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
