An Integrated Flow from pre-Silicon Simulation to post-Silicon Verification

This paper presents an integrated flow to bridge the existing gap from pre-silicon simulation to post-silicon verification environments. This flow features automatic reproduction in lab of the test-bench used in simulation and sharing of data between design and test environments. A Design For Testability (DFT) approach has been also used to increase the controllability and observability of the system. This integrated flow has been successfully used to validate a mixed-signal IC developed by SensorDynamicsAG for sensor conditioning leading to time and cost reduction and to an increased reliability and quality of the overall test phase (simulation and verification).