Design and Validation of Digital Channels for a Galileo Receiver Prototype

This paper describes the design activity for the digital baseband processing of a prototype receiver for the Galileo system. According to the applied hardware-software partitioning, the high rate elaborations have been implemented on a dedicated hardware, a Xilinx Virtex2 FPGA, while the remaining low rate processing has been programmed on an Analog Device DSP. A customarily designed prototype board has been used to validate the receiver under real working conditions: a dynamic GPS and Galileo scenarios. Particularly, the paper focus on the receiver Digital Channel, which is the critical core of the FPGA, from VHDL modeling to hardware implementation and testing.