PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing

In the last decades, FPGAs have been increasingly used in many different mission critical applications, such as the avionics and aerospace ones. Thus, research interest in studying faults in FPGAs has seen a sharp increase, especially for those applications that require high dependability and must operate in harsh environments. The increase of resources available in FPGA devices has caused a huge growth in routing complexity. Nowadays, more than 80% of transistors in modern FPGAs are related to the routing infrastructure. The analysis of faults related to routing structure of FPGA devices is a hard task due to the lack of tools working at low-level, limited information availability about interconnection structure from vendors and, above all, no automated testing workflow for such kind of resources. In this paper, we introduce PyXEL, an integrated environment realized to automatize the analysis of fault effects in FPGAs routing structure. PyXEL is a Python-based framework that allows to easily manipulate FPGAs bitstreams in order to inject specific faults and to analyze their behavior. Moreover, PyXEL provides an easy way to build and run experimental workflow interacting directly with Xilinx Vivado and ISE allowing to select routing resources to test and logically analyze results. We demonstrated the feasibility and the advantages of our approach exploiting PyXEL to gain insight into the electrical effects of faults in the routing interconnections of the Xilinx Artix-7.