CCSDS 131.2-B-1 Frequency Estimation Trade-Offs and a Novel Multi-Algorithm FPGA Architecture

In recent years, following the rapid innovation guidelines of most space agencies, there have been major advances in satellite transmitter technologies. Released in 2012, the CCSDS 131.2-B-1 is one of the most recent downlink standards, with lacking in-depth research, but strongly endorsed by the European Space Agency (ESA). It seems then important to evaluate the performance of different frequency error detectors (FED) on its specific frame structure. This paper firstly deals with the analysis of the most common FEDs, while in the second part it proposes a lightweight architecture to estimate and compensate the carrier error using different algorithms on the same FPGA implementation. Specifically, the Delay Multiply, Kay, Fitz, Luise Reggiannini, Mengali Morelli, and O'Shea et al. estimators are evaluated for both the estimation range and the accuracy. Following the general trade-offs, the design and implementation of the multi-algorithm estimator are detailed for a single feedback loop receiver. The system implements the Mengali Morelli algorithm in the initial acquisition phase to exploit its wide estimation range, while it implements the Fitz algorithm for the tracking phase to take advantage of the lower RMS frequency error. The implementation follows a serial pipelined architecture, which can provide a new estimate for both algorithms in 5205 clock cycles using 942 LUT, 918 FF, 2.5 BRAM, and 7 DSP on a Xilinx Virtex 7 FPGA. Together with the frequency error detector specifications, the entire acquisition and tracking loop is reported, which shows an output RMS frequency error of about 1.05 kHz at 8.5 Mbaud and 50 kHz/s Doppler rate, that can be easily compensated by a common pilot-assisted phase estimator.