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EnglishDuring synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small while circuits with low depth are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100% testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth.
| Titolo: | On the Construction of Small Fully Testable Circuits with Low Depth |
| Autori interni: | |
| Anno del prodotto: | 2007 |
| Abstract: | During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small while circuits with low depth are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100% testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth. |
| Handle: | http://hdl.handle.net/11568/113215 |
| ISBN: | 076952978X |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
http://hdl.handle.net/11568/113215
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