Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design problem due to the limited number of available pins (in not Ball Grid Array package) and to the common need of a frequency reduction, especially into systems that require an external System on Programmable Chip (SoPC). In this paper, an ASIC solution based on bisynchronous FIFO structures for frequency conversion is presented. The proposed bridge involves a custom protocol for the conversion of the transmitted data in low frequency and low width bus. Moreover, it allows managing data transmission with two different priority levels. The module is AHB lite compliant with a number of pins equal to the width of the FIFOs (configurable during implementation phase) and two handshaking signals. Output clock frequency and internal FIFOs dimension are user-defined too.
Pin-limited frequency downscaler AHB bridge for ASIC to FPGA communication
FANUCCI, LUCA;
2008-01-01
Abstract
Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design problem due to the limited number of available pins (in not Ball Grid Array package) and to the common need of a frequency reduction, especially into systems that require an external System on Programmable Chip (SoPC). In this paper, an ASIC solution based on bisynchronous FIFO structures for frequency conversion is presented. The proposed bridge involves a custom protocol for the conversion of the transmitted data in low frequency and low width bus. Moreover, it allows managing data transmission with two different priority levels. The module is AHB lite compliant with a number of pins equal to the width of the FIFOs (configurable during implementation phase) and two handshaking signals. Output clock frequency and internal FIFOs dimension are user-defined too.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
