A Novel High-Performance Parallel-Type Slew-Rate Enhancer for LCD-Driving Applications

In applications requiring fast driving of large capacitive loads, such as LCD-driving, amplifier design is bound to implement Slew-Rate Enhancement (SRE) techniques. In this work, we investigate performances of a single-stage amplifier coupled with a parallel SRE circuit. Operating versatility and design simplicity make the parallel SRE approach noteworthy, since such features are not always guaranteed by previously proposed solutions. An improved version of an existing parallel SRE architecture is presented and thoroughly examined, through electrical simulations of a 0.18 μm CMOS design. Rail-to-rail driving capability of a 1 nF capacitive load was assessed. Slew rate and 1%-settling time equal to 752 V/ms and 4.69 μs, respectively, were obtained with a 4 μA total quiescent current. Such preliminary results confirm the proposed approach to be a viable solution for low-power high-speed amplifier design.