This paper presents a 0.8-mW 0.2-mm2 9-level second-order single-loop SC Delta-Sigma modulator (ΔΣM) ADC in 1.8-V 0.18-μm CMOS technology for low-power high-resolution sensing applications. The ΔΣM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dBFS input for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOMS. The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10-μW resistor-less flash quantizer. The obtained 172.6-dB FOMS is competitive within the state-of-art high-resolution (SNDR > 90 dB) and general-purpose (bandwidth > 20 kHz) SC ΔΣM ADCs.

A 0.8MW 50kHz 94.6DB-SNDR bootstrapping-free SC delta-sigma modulator ADC with flicker noise cancellation

Dei M.;
2021-01-01

Abstract

This paper presents a 0.8-mW 0.2-mm2 9-level second-order single-loop SC Delta-Sigma modulator (ΔΣM) ADC in 1.8-V 0.18-μm CMOS technology for low-power high-resolution sensing applications. The ΔΣM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dBFS input for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOMS. The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10-μW resistor-less flash quantizer. The obtained 172.6-dB FOMS is competitive within the state-of-art high-resolution (SNDR > 90 dB) and general-purpose (bandwidth > 20 kHz) SC ΔΣM ADCs.
2021
978-1-7281-9201-7
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/1206167
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