Analysis and Simulation of a PLL Architecture Towards a Fully Integrated 65 nm Solution for the New Spacefibre Standard

This paper presents the modeling and design activity of a PLL (Phase-Locked Loop) architecture to generate the clock reference for the new ESA Spacefibre standard for on-board satellite communications up to 6.25 Gbps. Starting from a 6.25 GHz VCO rad-hard design, integrated in 65 nm technology within an IMEC-University of Pisa collaboration, this work presents a PLL architecture including configurable integer divider, down to a reference signal of 156.25 MHz, phase-frequency detector, charge pump and passive loop filter. Modeling and simulation analysis, carried out in Keysight ADS environment, show that a fully integrated solution can be achieved with a 6 MHz low-pass PLL loop filter whose passive devices can be integrated on chip with an area of about 4600 µm2. The PLL phase noise performance are in line with that of the original VCO, and for the stability a gain and phase margins of 86 dB and 50° are achieved. PLL lock time is about 555 ns. A preliminary circuit for the charge pump implementation is also proposed.