Power Aware Scheduling of Tasks on FPGAs in Data Centers

A variety of computing platforms like Field Pro- grammable Gate Array (FPGA), Graphics Processing Unit (GPU) and multicore Central Processing Unit (CPU) in data centers are suitable for acceleration of data-intensive workloads. Especially, FPGA platforms in data centers are gaining popularity for high- performance computations due to their high speed, reconfig- urable nature and cost-effectiveness. Such heterogeneous, highly parallel computational architectures in data centers, combined with high-speed communication technologies like 5G, are be- coming increasingly suitable for real-time applications. However, flexibility, cost-effectiveness, high computational capabilities, and energy efficiency remain challenging issues in FPGA based data centers. This paper introduces a power-aware scheduling methodology aimed at accommodating periodic hardware tasks within the available FPGAs of a data center at their potentially maximum speed. This proposed methodology guarantees the execution of these tasks using the maximum number of parallel computation units possible to implement in the FPGAs, with minimum power consumption. The proposed scheduling method- ology is implemented in a data center with multiple Alveo − 50 X ilinx − AM D FPGAs and V itis 2023 tool. The evidence from the implementation shows the proposed scheduling methodology is efficient compared to existing solutions.