Fast minimization time, compact area low delay are important issues in logic circuit design. In order to orchestrate these main goals, in this paper we propose a new four level logic circuit (Generalized EXOR- Projected Sum of Products, in short GEP-SOP) with low delay and compact area. Even if the problem of finding an optimal GEP-SOPs is computationally hard, we propose an efficient approximation algorithm that gives guaranteed near optimal solutions. A wide set of experimental results confirms that the GEP-SOP forms are often more compact than the SOP forms, and their synthesis is always a very fast reoptimization phase after SOP minimization.
An Approximation Algorithm for Generalized EXOR Projected Sum of Products
BERNASCONI, ANNA;
2008-01-01
Abstract
Fast minimization time, compact area low delay are important issues in logic circuit design. In order to orchestrate these main goals, in this paper we propose a new four level logic circuit (Generalized EXOR- Projected Sum of Products, in short GEP-SOP) with low delay and compact area. Even if the problem of finding an optimal GEP-SOPs is computationally hard, we propose an efficient approximation algorithm that gives guaranteed near optimal solutions. A wide set of experimental results confirms that the GEP-SOP forms are often more compact than the SOP forms, and their synthesis is always a very fast reoptimization phase after SOP minimization.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
