FPGA-based acceleration of QC-LDPC syndrome encoding for QKD systems

Quantum Key Distribution (QKD) systems will be fundamental in ensuring secure communications in future networks. However, due to device imperfections and the random nature of quantum physics itself, these systems need an information reconciliation phase to correct for errors in the key exchange. In particular, for Continuous Variable QKD (CV-QKD) systems, it is possible to employ Multi-Dimensional Reconciliation (MDR) with Quasi-Cyclic LDPC (QC-LDPC) error correction codes. To achieve good reconciliation with low SNR or to limit finite size effects, large input block codes should be employed. FPGA acceleration is here envisioned. In this work we implemented the encoding for syndromes as large as 1Mbit with a QC-LDPC lift factor of 512 bits and achieve a throughput exceeding 3.55 Gb/s.