Single-Branch NMOS-Only Self-Cascoded Voltage Reference Operating Down to 0.28-V Supply

To enable the onset of next-generation technologies, pushing electronic designs down to minimal supply voltage and power consumption levels is of capital importance. In this work, we present a single-branch 3-transistor voltage reference, enhancing an existing circuit topology through the addition of a novel self-cascode technique. Extensive post-layout simulations of a 0.18-μ m CMOS design highlighted compliance to supply voltages as low as 0.28 V with a nominal reference voltage of Vref =0.171 V, while mantaining robustness to process-voltage-temperature variations. Specifically, the line sensitivity is equal to 0.089 % / V, the temperature coefficient is 39.63 ppm / °C from -20 °C to 80 °C and the relative standard deviation of Vref is equal to 5.3%, evaluated from Monte Carlo statistical simulations. Power consumption is as low as 49.3 pW in nominal conditions and the area occupation is equal to only 0.00024 mm2. These findings appoint the proposed circuit as an appealing solution for compact, robust, low-voltage and low-power voltage reference implementations.