Sorting Errors Effects on Optimal Combination Algorithms for Digital-to-Analog Converters

Digital-to-Analog Converters (DACs) suffer from static non-linearity due to mismatch errors affecting their unit elements. Optimal Combination Algorithms (OCAs) mitigate this issue by rearranging the switching sequence of the unit elements to minimize Integral Non-Linearity (INL). However, sorting errors caused by comparator imperfections may degrade OCA effectiveness. This work systematically analyzes the effects of random comparator offset on various OCA techniques, considering five different sorting algorithms as part of the OCAs: bubble sort, selection sort, insertion sort, merge sort and quick sort. Monte Carlo simulations of a 6-bit DAC have been executed to assess the post-OCA INL performance obtained with each approach. Results indicate that for high-performance OCAs the choice of the sorting algorithm has minimal impact. Conversely, for less efficient OCAs, selection sort exhibits superior INL performance at higher comparator errors. These findings highlight the trade-offs between sorting algorithm choice, computational complexity and post-OCA DAC accuracy.