This paper describes the architecture of a flexible and reconfigurable processor for the computation of the state-metric recursion in a multi-standard BCJR decoder. The unit can serve binary as well as duo-binary codes with any number of states. The architecture is arranged into a cluster of state-metric processors plus two multiplexing networks for feedback and normalization, configured on-the-fly for the code in use. An optimized solution is presented allowing the support of every code among 8-state duo-binary, 8-state binary and 2-state binary codes, i.e., of every Turbo and LDPC code defined by the modern communication standards. The logical synthesis on different CMOS technologies shows that the architecture attains a maximum clock frequency of 450 MHz. Finally, the complexity overhead of such a flexible design is only about 18% w.r.t. optimized single-standard solutions.
A Flexible State-Metric Recursion Unit for a Multi-Standard BCJR Decoder
ROVINI, MASSIMO;FANUCCI, LUCA
2009-01-01
Abstract
This paper describes the architecture of a flexible and reconfigurable processor for the computation of the state-metric recursion in a multi-standard BCJR decoder. The unit can serve binary as well as duo-binary codes with any number of states. The architecture is arranged into a cluster of state-metric processors plus two multiplexing networks for feedback and normalization, configured on-the-fly for the code in use. An optimized solution is presented allowing the support of every code among 8-state duo-binary, 8-state binary and 2-state binary codes, i.e., of every Turbo and LDPC code defined by the modern communication standards. The logical synthesis on different CMOS technologies shows that the architecture attains a maximum clock frequency of 450 MHz. Finally, the complexity overhead of such a flexible design is only about 18% w.r.t. optimized single-standard solutions.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
