This paper presents a high-level design methodology for AC-coupled Gm-C biquad filters tailored for power-line communication (PLC) systems, specifically addressing the stringent requirements of battery monitoring applications (BMA). We analyze two standard biquad topologies, the Passive-Feedback Biquad (PFB) and the Active-Feedback Biquad (AFB), deriving key design equations and evaluating their performance characteristics relevant to BMA. Focusing on system-level perspective, we explore trade-offs between digital tunability and modularity for optimizing design effort in multichannel systems where different battery modules are coupled to a shared power network. In addition, we discuss the impact of parasitic capacitance, the finite output resistance of the filter transconductors, and the input impedance characteristics of both topologies, leading to clear design indications. Our findings offer valuable insight for designing efficient and adaptable analog front-end circuits for PLC networks.

High-Level Design of AC-Coupled Gm-C Biquads for Power-Line Communication

Nannipieri I.
Primo
;
Gagliardi F.
Secondo
;
Dei M.
Ultimo
2025-01-01

Abstract

This paper presents a high-level design methodology for AC-coupled Gm-C biquad filters tailored for power-line communication (PLC) systems, specifically addressing the stringent requirements of battery monitoring applications (BMA). We analyze two standard biquad topologies, the Passive-Feedback Biquad (PFB) and the Active-Feedback Biquad (AFB), deriving key design equations and evaluating their performance characteristics relevant to BMA. Focusing on system-level perspective, we explore trade-offs between digital tunability and modularity for optimizing design effort in multichannel systems where different battery modules are coupled to a shared power network. In addition, we discuss the impact of parasitic capacitance, the finite output resistance of the filter transconductors, and the input impedance characteristics of both topologies, leading to clear design indications. Our findings offer valuable insight for designing efficient and adaptable analog front-end circuits for PLC networks.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/1337747
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