Evaluating Performance in On-Chip Networks with Network Calculus

Multi-core system-on-a-chip (SoC) architectures increasingly rely on networks-on-chip (NoCs) as their primary communication infrastructure. This shift aims to address the performance and scalability constraints associated with traditional bus-based and point-to-point communication architectures. To enhance performance, ensure quality of service (QoS), and overcome NoC-related constraints, it is essential to closely monitor traffic flows within the on-chip network. Network calculus provides a mathematical approach for evaluating performance assurances in on-chip networking systems. In this research paper, we propose a network calculus-based approach to analyze the performance of sampled traffic in on-chip networks to improve throughput, reduce end-to-end latency, ensure the quality of service, and architectural design. Additionally, the derived performance results have been compared with existing research based on queuing theory (QT), recursive calculus (RC), and network calculus (NC). This comparison shows a significant improvement in the accuracy of performance over existing methods