Performance Analysis of Homogeneous and Heterogeneous Network-on-Chip Architectures

Performance analysis of on-chip networks has become a critical aspect of designing and enhancing the capability of multiprocessor system-on-chip architectures. As system-on-chips continue to scale in complexity, adding more features and modules, the networks-on-chip plays a vital role in ensuring the system meets its performance targets by enabling efficient data transfer within the chip. In this paper, we present an approach to evaluate performance metrics such as throughput, packet success and loss rates, end-to-end latency, data transfer latency, resource arbitration latency, head-flit source dequeuing latency, and link utilization for network-on-chip (NoC) systems. Moreover, we use deterministic network calculus to analyze the worstcase performance bounds of NoC systems. Compared to existing approaches based on stochastic network calculus, recursive calculus, and network calculus, our proposed approach demonstrates better performance. The proposed approach yields tighter performance bounds and improved performance metrics, which can support more efficient NoC design and enhanced overall performance.