A Network Calculus Approach to Performance Analysis in Wormhole Network-on-Chips

Recent advancements in industry underscore the growing demand for systems that provide both high computational performance and real-time assurances, despite these objectives traditionally being seen as conflicting. To support the complex task of designing such Network-on- Chip (NoC) systems with both performance and Quality of Service (QoS) requirements, frameworks such as ARM MPAM envisage systems with hardware support for resource partitioning and the observation of its effects. It enables new application areas for traditional QoS techniques. Network Calculus (NC) uses transformation operations to model traffic profiles through network nodes. It enables the estimation of the minimum service guaranteed to a flow as it moves through flow-controlled nodes. This paper proposes using Network Calculus to derive insights from traces of traffic samples and to evaluate service curves for QoS validation and worst-case delay analysis in NoC architectures. The derived worst-case performance bound is compared with existing works based on Queueing Theory (QT) and Network Calculus (NC). This comparison demonstrates a significant improvement in the accuracy of the delay bounds over the existing QT and NC approaches.