This paper describes the first complete design of a single-core multi-standard flexible Turbo/LDPC decoder using an ASIC approach. Such a solution outperforms other state-of-the-art implementations based on application-specific instruction-set processors (ASIPs), which are shown to sufTer from impaired throughput and power consumption. In this paper, we describe in detail the VLSI flexible architecture of a decoder coping with all the moderu communication standards defining LDPC and Turbo codes, and provide a proof-of-concept implementation complaint with 3GPP-HSDPA, DVB-SH, IEEE 802.16e and IEEE 802.11n standards. The decoder, running at only 150 MHz for a reduced power, occupies an area of 0.9mm2 with a maximum power consumption of only 86.1 mW.
A Multi-Standard Flexible Turbo/LDPC Decoder via ASIC Design
ROVINI, MASSIMO;FANUCCI, LUCA
2010-01-01
Abstract
This paper describes the first complete design of a single-core multi-standard flexible Turbo/LDPC decoder using an ASIC approach. Such a solution outperforms other state-of-the-art implementations based on application-specific instruction-set processors (ASIPs), which are shown to sufTer from impaired throughput and power consumption. In this paper, we describe in detail the VLSI flexible architecture of a decoder coping with all the moderu communication standards defining LDPC and Turbo codes, and provide a proof-of-concept implementation complaint with 3GPP-HSDPA, DVB-SH, IEEE 802.16e and IEEE 802.11n standards. The decoder, running at only 150 MHz for a reduced power, occupies an area of 0.9mm2 with a maximum power consumption of only 86.1 mW.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
