The integration of a Low Noise Amplifier (LNA) with on-chip antenna for 60 GHz short-range wireless applications is discussed in the paper. A 65 nm CMOS Silicon-on-Insulator (SOI) technology has been selected as target. With respect to the state of the art, the on-chip co-design of LNA and antenna permits avoiding a pre-defined constraint of 50 Ohm impedance matching. By relaxing the impedance matching specification a LNA with only two amplification stages has been designed to reach the desired power gain (>;20 dB) and noise figure (<; 5 dB) with a power consumption and circuit complexity optimized vs. state-of-art LNAs with similar performances. A dipole antenna with coplanar strip feed has been also designed matching the 20 Ohm input LNA impedance and allowing an extra gain of 3 dB at 60 GHz with a limited on-chip area occupation
Design of a Low Noise Amplifier with integrated antenna for 60 GHz wireless communications
SAPONARA, SERGIO;FANUCCI, LUCA;NERI, BRUNO
2011-01-01
Abstract
The integration of a Low Noise Amplifier (LNA) with on-chip antenna for 60 GHz short-range wireless applications is discussed in the paper. A 65 nm CMOS Silicon-on-Insulator (SOI) technology has been selected as target. With respect to the state of the art, the on-chip co-design of LNA and antenna permits avoiding a pre-defined constraint of 50 Ohm impedance matching. By relaxing the impedance matching specification a LNA with only two amplification stages has been designed to reach the desired power gain (>;20 dB) and noise figure (<; 5 dB) with a power consumption and circuit complexity optimized vs. state-of-art LNAs with similar performances. A dipole antenna with coplanar strip feed has been also designed matching the 20 Ohm input LNA impedance and allowing an extra gain of 3 dB at 60 GHz with a limited on-chip area occupationI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
