In this paper a new Intellectual Property (IP) VLSI architecture for the implementation of real time and low complexity fast motion estimation for. multimedia applications is proposed. The motion estimation is a kev issue either in H.263/MPEG video coding ol in image filtering. Specially, the algorithms bused on the predictive spatio-temporal technique achieve high coding quality at reasonable computational power by exploiting the spatio-temporal correlation of the video motion field. The novel architecture, obtained by a design-reuse methodology: is parametric and configurable and hence it allows for the implementation of different predictive algorithms. Ir also features hardware complexity scalability and it is suitable for the design of ASICs optimized for a wide range of multimedia applications. The IF, synthesized for a 0.25 mum CMOS technology: achieves a computational power lip to 740x10(6) absolute differences per second, for a maximum 0.96 mm(2) core size, and permits the processing of typical video images at clock frequencies of few MHz.
IP reuse VLSI architecture for low complexity fast motion estimation in multimedia applications
FANUCCI, LUCA;SAPONARA, SERGIO;
2000-01-01
Abstract
In this paper a new Intellectual Property (IP) VLSI architecture for the implementation of real time and low complexity fast motion estimation for. multimedia applications is proposed. The motion estimation is a kev issue either in H.263/MPEG video coding ol in image filtering. Specially, the algorithms bused on the predictive spatio-temporal technique achieve high coding quality at reasonable computational power by exploiting the spatio-temporal correlation of the video motion field. The novel architecture, obtained by a design-reuse methodology: is parametric and configurable and hence it allows for the implementation of different predictive algorithms. Ir also features hardware complexity scalability and it is suitable for the design of ASICs optimized for a wide range of multimedia applications. The IF, synthesized for a 0.25 mum CMOS technology: achieves a computational power lip to 740x10(6) absolute differences per second, for a maximum 0.96 mm(2) core size, and permits the processing of typical video images at clock frequencies of few MHz.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
