Real-time Earth observation has become essential for many applications such as natural disasters monitoring, coastal maritime surveillance and winter navigation in polar seas. In this respect the European Space Agency (ESA) has recently proposed the so called on-board SAR processing system (OSPS) which needs powerful real-time DSP and FFT processors to be implemented in rad-hard technology. In this paper a VLSI single chip programmable FFT processor suitable for the ESA OSPS is presented. The FFT processor is able to process 32, 64, 128 and 256 complex points FFT, with an input data rate of 50 Mcomplexsample/s. For low-cost proof-of-concept prototyping the chip was designed in 0.6 μm CMOS technology yielding an overall core area of 36.09 mm2 for about 43 Kgate and demonstrated to be fully functional by extensive computer simulations
Single-chip mixed-radix FFT processor for real-time on-board SAR processing
FANUCCI, LUCA;
1999-01-01
Abstract
Real-time Earth observation has become essential for many applications such as natural disasters monitoring, coastal maritime surveillance and winter navigation in polar seas. In this respect the European Space Agency (ESA) has recently proposed the so called on-board SAR processing system (OSPS) which needs powerful real-time DSP and FFT processors to be implemented in rad-hard technology. In this paper a VLSI single chip programmable FFT processor suitable for the ESA OSPS is presented. The FFT processor is able to process 32, 64, 128 and 256 complex points FFT, with an input data rate of 50 Mcomplexsample/s. For low-cost proof-of-concept prototyping the chip was designed in 0.6 μm CMOS technology yielding an overall core area of 36.09 mm2 for about 43 Kgate and demonstrated to be fully functional by extensive computer simulationsI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
