Evaluating Optimizations for Multiprocessors E-Commerce Server Running TPC-W Workload

In this paper, the performance of an Electronic Commerce server, i.e. a system running Electronic Commerce applications is evaluated in the case of shared-bus multiprocessor architecture. In particular, we focused on the memory subsystem design and the analysis of coherence related overhead when the running software is setup as specified in the TPC-W benchmark. Our aim is to individuate main factors that limit performance in such system, and the main optimization that can be done to speed-up the execution of ECommerce workload on SMP architecture. Our results show that: i) we need an accurate redesign of kernel data structure for large cache size; ii) cache affinity is useful in reducing cold and replacement miss, but it is not effective in every load-conditions; iii) passive sharing, i.e. the sharing induced by process migration, is a cause of performance degradation. A Write-Update protocol that correctly treats passive sharing (namely PSCR) permits two beneficial effects: increases performance in every situation and increases system scalability (up to 20 processor are permitted in our configuration)