Exploring the VLSI Design Space for Low Power DCT/IDCT Macro Cells

In this paper we explore the architectural and technological VLSI design space in order to obtain two Intellectual Property DCT/IDCT macro cells reaching low power and flexibility. The cells have been implemented on different CMOS technologies to assess their reusability and then they have been fully characterized in terms of area, throughput and power consumption. The relevant results demonstrate that the use of a parallel approach and of a high speed technology library is suitable for large image formats to achieve real time and low power constraints in highly integrated multimedia terminals. On the other hand for small formats, typical of mobile video telephony terminals, a hardware multiplexing approach and the use of a low leakage library grant a better area-power tradeoff. The power dissipation achieved, 11 mW for a MPEG video resolution, is very interesting when compared to known hardware and software based solutions.