VLIW architectures have been shown to be able to exploit large amounts of find grain parallelism in the execution of sequential imperative programs. In this paper, a new computing model is presented, which allows the VLIW techniques to be adopted to operate a distributed memory, multiprocessor machine. The model, called VLIW-in-the-large, can be adopted in conjunction with a suitable hardware framework to obtain consistent speedups in the execution of both sequential and parallel-natured software. The authors show that the advantages of the VLIW-in-the-large computing model with respect to the classical VLIW approach are: (i) better utilization of hardware resources; (ii) extension of the applicability of the VLIW techniques to multiprocessor architectures, in such a way that they can be used for multi-style, multi-grain parallelism exploitation; (iii) compact realization of processing elements, suitable for VLSI massively parallel architectures

VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors

DANELUTTO, MARCO;VANNESCHI, MARCO
1990

Abstract

VLIW architectures have been shown to be able to exploit large amounts of find grain parallelism in the execution of sequential imperative programs. In this paper, a new computing model is presented, which allows the VLIW techniques to be adopted to operate a distributed memory, multiprocessor machine. The model, called VLIW-in-the-large, can be adopted in conjunction with a suitable hardware framework to obtain consistent speedups in the execution of both sequential and parallel-natured software. The authors show that the advantages of the VLIW-in-the-large computing model with respect to the classical VLIW approach are: (i) better utilization of hardware resources; (ii) extension of the applicability of the VLIW techniques to multiprocessor architectures, in such a way that they can be used for multi-style, multi-grain parallelism exploitation; (iii) compact realization of processing elements, suitable for VLSI massively parallel architectures
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/200834
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