The single-chip integration of antenna and Low Noise Amplifier (LNA) for 60 GHz short-range wireless transceivers is presented in this work. A 65 nm CMOS Silicon-on-Insulator (SOI) technology has been selected as target; due to its high-resistivity substrate the losses are drastically reduced if compared with the bulk silicon technology and more energy will be provided to the on-chip antenna to radiate. Two different LNA architectures are proposed. First, a three-stage LNA with conventional 50 Ohm input matching allows for a power gain of 23 dB, a noise figure (NF) of 4.04 dB and a power consumption of 35 mW. By relaxing the impedance matching specification, due to on-chip co-design of amplifier and antenna, a new LNA with only two amplification stages has been designed. The two-stage LNA achieves similar performance of the three-stage one (gain >;22 dB, NF<; 5 dB) with a power consumption reduced by 25%. A dipole antenna with coplanar strip feed has been also designed matching the input LNA impedance and allowing an antenna gain of 3.22 dB at 60 GHz with a limited on-chip area occupation
60-GHz single-chip integrated antenna and Low Noise Amplifier in 65-nm CMOS SOI technology for short-range wireless Gbits/s applications
SAPONARA, SERGIO;FANUCCI, LUCA;NERI, BRUNO
2011
Abstract
The single-chip integration of antenna and Low Noise Amplifier (LNA) for 60 GHz short-range wireless transceivers is presented in this work. A 65 nm CMOS Silicon-on-Insulator (SOI) technology has been selected as target; due to its high-resistivity substrate the losses are drastically reduced if compared with the bulk silicon technology and more energy will be provided to the on-chip antenna to radiate. Two different LNA architectures are proposed. First, a three-stage LNA with conventional 50 Ohm input matching allows for a power gain of 23 dB, a noise figure (NF) of 4.04 dB and a power consumption of 35 mW. By relaxing the impedance matching specification, due to on-chip co-design of amplifier and antenna, a new LNA with only two amplification stages has been designed. The two-stage LNA achieves similar performance of the three-stage one (gain >;22 dB, NF<; 5 dB) with a power consumption reduced by 25%. A dipole antenna with coplanar strip feed has been also designed matching the input LNA impedance and allowing an antenna gain of 3.22 dB at 60 GHz with a limited on-chip area occupationI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
