Two architectures for cost-effective and real-time implementation of non-linear image and video filters are presented in the paper. The first architecture is a traditional VHDL-based ASIC (Application Specific Integrated Circuit) design while the second one is an ADL (Architecture Description Language) based ASIP (Application Specific Instruction Set Processor). A system to improve the visual quality of images, based on Retinex-like algorithm, is referred as case study. First, starting from a high-level functional description the design space is explored to achieve a linearized structural C model of the algorithm with finite arithmetic precision. For the algorithm design space exploration visual and complexity criteria are adopted while a statistical analysis of typical input images drives the algorithm optimization process. The algorithm is implemented both as ASIC and ASIP solution in order to explore the trade-off between the flexibility of a software solution and the power and complexity optimization of a dedicated hardware design. The aim is to achieve the desired algorithmic functionality and timing specification at reasonable complexity and power costs. Taking advantage of the processor programmability, the flexibility of the system is increased, involving e.g. dynamic parameter adjustment and color treatment. Gate level implementation results in a 0.18μm standard-cell CMOS technology are presented for both the ASIC and ASIP approach.

Design of Application Specific Instruction-Set Processor for image and video filtering

SAPONARA, SERGIO;FANUCCI, LUCA;
2006

Abstract

Two architectures for cost-effective and real-time implementation of non-linear image and video filters are presented in the paper. The first architecture is a traditional VHDL-based ASIC (Application Specific Integrated Circuit) design while the second one is an ADL (Architecture Description Language) based ASIP (Application Specific Instruction Set Processor). A system to improve the visual quality of images, based on Retinex-like algorithm, is referred as case study. First, starting from a high-level functional description the design space is explored to achieve a linearized structural C model of the algorithm with finite arithmetic precision. For the algorithm design space exploration visual and complexity criteria are adopted while a statistical analysis of typical input images drives the algorithm optimization process. The algorithm is implemented both as ASIC and ASIP solution in order to explore the trade-off between the flexibility of a software solution and the power and complexity optimization of a dedicated hardware design. The aim is to achieve the desired algorithmic functionality and timing specification at reasonable complexity and power costs. Taking advantage of the processor programmability, the flexibility of the system is increased, involving e.g. dynamic parameter adjustment and color treatment. Gate level implementation results in a 0.18μm standard-cell CMOS technology are presented for both the ASIC and ASIP approach.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11568/202876
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