A switched capacitor DAC, capable of producing a continuous time output signal, is presented. The multiphase conversion cycle allows cancellation of the input offset and low frequency noise of both op-amps used in the circuit. Electrical simulations, performed on a 12 bit prototype, designed by means of UMC 0.18 um MM/RF CMOS process, are shown. The main estimated performances are: 2.4 us conversion time, 0.42 mW power consumption at 1.8 V power supply, 0.49 mV rms output noise over a 400 kHz bandwidth

A continuous time switched capacitor DAC with offset and flicker noise cancellation

LONGHITANO, AURELIO NUNZIO;DEL CESTA, FRANCESCO;BRUSCHI, PAOLO;
2013

Abstract

A switched capacitor DAC, capable of producing a continuous time output signal, is presented. The multiphase conversion cycle allows cancellation of the input offset and low frequency noise of both op-amps used in the circuit. Electrical simulations, performed on a 12 bit prototype, designed by means of UMC 0.18 um MM/RF CMOS process, are shown. The main estimated performances are: 2.4 us conversion time, 0.42 mW power consumption at 1.8 V power supply, 0.49 mV rms output noise over a 400 kHz bandwidth
9781467345804
9781467345811
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/278744
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