The Silicon-Vertex-Trigger (SVT) is a processor developed at CDF experiment to perform online fast and precise track reconstruction. SVT is made of two pipelined processors: the Associative Memory finds low precision tracks looking for coincidences between hits from the tracking detectors and track candidates (roads) stored in memory; the Track Fitter refines the track quality whith high precision fits. The GigaFitter is a next generation track fitter, developed to reduce the degradation of the SVT efficiency due to the increasing instantaneous luminosity. It reduces the track parameter reconstruction to a few clock cycles and can perform many fits in parallel, thus allowing high resolution tracking at very high rate. The core of the GigaFitter is implemented in a modern Xilinx Virtex-5 FPGA chip, rich of powerful DSP arrays. With respect to the current Track Fitter, the GigaFitter is faster and provided of much more memory to store a greater number of roads to be used in the fit; this results in an increased SVT efficiency as more track candidates can be reconstructed. The GigaFitter has been installed in parasitic mode at CDF and has been tested against the current Track Fitter. We will describe the GigaFitter architecture, the parasitic installation at CDF and the performances with respect to the current system.
The GigaFitter: A next generation track fitter to enhance online tracking performances at CDF2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)
DELL'ORSO, MAURO;
2009-01-01
Abstract
The Silicon-Vertex-Trigger (SVT) is a processor developed at CDF experiment to perform online fast and precise track reconstruction. SVT is made of two pipelined processors: the Associative Memory finds low precision tracks looking for coincidences between hits from the tracking detectors and track candidates (roads) stored in memory; the Track Fitter refines the track quality whith high precision fits. The GigaFitter is a next generation track fitter, developed to reduce the degradation of the SVT efficiency due to the increasing instantaneous luminosity. It reduces the track parameter reconstruction to a few clock cycles and can perform many fits in parallel, thus allowing high resolution tracking at very high rate. The core of the GigaFitter is implemented in a modern Xilinx Virtex-5 FPGA chip, rich of powerful DSP arrays. With respect to the current Track Fitter, the GigaFitter is faster and provided of much more memory to store a greater number of roads to be used in the fit; this results in an increased SVT efficiency as more track candidates can be reconstructed. The GigaFitter has been installed in parasitic mode at CDF and has been tested against the current Track Fitter. We will describe the GigaFitter architecture, the parasitic installation at CDF and the performances with respect to the current system.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
