We propose a new generation of VLSI processor for pattern recognition based on Associative Memory architecture, optimized for on-line track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new R&D Associative Memory project: it maximizes the pattern density on ASICs and improves the functionality for the Fast Tracker (FTK) proposed to upgrade the ATLAS trigger at LHC.
Titolo: | Associative memory design for fast tracker at LHC2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC) |
Autori interni: | |
Anno del prodotto: | 2009 |
Rivista: | |
Abstract: | We propose a new generation of VLSI processor for pattern recognition based on Associative Memory architecture, optimized for on-line track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new R&D Associative Memory project: it maximizes the pattern density on ASICs and improves the functionality for the Fast Tracker (FTK) proposed to upgrade the ATLAS trigger at LHC. |
Handle: | http://hdl.handle.net/11568/538956 |
ISBN: | 9781424439614 |
Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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