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EnglishIn this paper, we propose a compilation tool-chain supporting the eective exploitation of multi-core architectures oering hundreds of cores. The tool-chain leverages on both the application requirements and the platform-specic features to provide developers with a powerful parallel-programming environment able to generate ecient parallel code. The design of parallel applications follows a semi-automatic approach enabling the programmer to transfer to back-end tools platform-specic code generation and optimization, thus making possible to avoid the clobbering of code with non-portable and complex directives. The programmer can graphically parallelize the application (mainly data-streaming ones) for the target platform using Thales' Spear Design Environment. The resulting parallelization is generated under the form of an Intermediate Representation, which is then passed to the back-end tools (HPC Project's Par4All) that generates efficient target code. We present the results obtained parallelizing a small subset of the RT-STAP radar algorithm and the Chirp filltering algorithm on standard multi-core and on nVidia GPUs.
| Titolo: | An innovative compilation tool-chain for embedded multi-core architectures | |
| Autori interni: | ||
| Anno del prodotto: | 2012 | |
| Abstract: | In this paper, we propose a compilation tool-chain supporting the eective exploitation of multi-core architectures oering hundreds of cores. The tool-chain leverages on both the application requirements and the platform-specic features to provide developers with a powerful parallel-programming environment able to generate ecient parallel code. The design of parallel applications follows a semi-automatic approach enabling the programmer to transfer to back-end tools platform-specic code generation and optimization, thus making possible to avoid the clobbering of code with non-portable and complex directives. The programmer can graphically parallelize the application (mainly data-streaming ones) for the target platform using Thales' Spear Design Environment. The resulting parallelization is generated under the form of an Intermediate Representation, which is then passed to the back-end tools (HPC Project's Par4All) that generates efficient target code. We present the results obtained parallelizing a small subset of the RT-STAP radar algorithm and the Chirp filltering algorithm on standard multi-core and on nVidia GPUs. | |
| Handle: | http://hdl.handle.net/11568/566469 | |
| ISBN: | 9783645500722 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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