The efficient parallelization of very ne-grained computations is an old problem still challenging also on modern shared memory architectures. Scalable parallelizations are possi ble if the base mechanisms provided by the run-time support (for inter-thread/inter-process synchronization/communication) are carefully designed and developed on top of parallel architec tures. This requires a deep knowledge of the hardware behavior and the interaction patterns used by the parallelism paradigms. In this paper we present our experience in developing e cient inter-thread interaction mechanisms on the THera TILEPr064 network processor. Although it is a domain-speci c parallel architecture, the TILEPr064 represents a notable example of how advanced architectural structures, such as user-accessible on chip interconnection networks and con gurable cache coherence protocols, are of great importance to design lightweight coop eration mechanisms enabling e cient parallel implementations of ne-grained problems. The paper presents our ideas and an experimental evaluation that compares our proposals with other existing run-time supports.
|Titolo:||Run-time mechanisms for fine-grained parallelism on network processors: The TILEPro64 experience|
|Anno del prodotto:||2014|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|