VLSI design of an high speed Turbo Decoder for 3rd generation satellite communication

In the present period in which 3rd generation systems including their satellite component are specified and realized, one important issue is to design a powerful channel coding scheme in order to ensure the good propagation of different types of information streams (voice, data) through the mobile satellite channel. In this field and in many other applications a new class of concatenated codes, called Turbo codes, have been introduced. Turbo coding scheme is able to achieve performance close to the Shannon's bound, but at the cost of a large transmission delay and decoder complexity. In this paper we propose the VLSI design of a Turbo decoder for high performance in terms of throughput and low latency time compliant with Third Generation Partnership Project (3GPP) specification. A 100 Mbit/s throughput has been demonstrated for an overall complexity of about 112 Kgates plus 35 Kbits dual port RAM and an operating clock frequency of 100 MHz.