In this paper the design and first measurements of a dual-processor embedded system for hand-held cartographic plotter are presented. The system study and relevant hardware/software partitioning are briefly addressed. As a result, two ARM710T cores together with several IPs connected by AHB bus have been integrated into a System-on-Chip. The main drivers for this architecture have been the computational power to reduce the cartographic map redraw time, the reduction of the overall power consumption, which is fundamental for any battery-powered device, and the compatibility with several kinds of LCDs, memories and standard interfaces. Finally, the ASIC design for a 0.35 m CMOS technology is presented. It results in a overall peak computational power of 66 MIPS @ 33MHz clock frequency, a standby power consumption of 20 mW for an overall area of 54.37 mm2. First measurements indicate an operating power consumption of 330 mW @ 25MHz. This figure can be reduced, for typical applications, by 50 % by means of the built-in power controller.

A Dual-Processor System-on-Chip for Electronics Cartographic Applications: A Design Case Study

FANUCCI, LUCA;
2002

Abstract

In this paper the design and first measurements of a dual-processor embedded system for hand-held cartographic plotter are presented. The system study and relevant hardware/software partitioning are briefly addressed. As a result, two ARM710T cores together with several IPs connected by AHB bus have been integrated into a System-on-Chip. The main drivers for this architecture have been the computational power to reduce the cartographic map redraw time, the reduction of the overall power consumption, which is fundamental for any battery-powered device, and the compatibility with several kinds of LCDs, memories and standard interfaces. Finally, the ASIC design for a 0.35 m CMOS technology is presented. It results in a overall peak computational power of 66 MIPS @ 33MHz clock frequency, a standby power consumption of 20 mW for an overall area of 54.37 mm2. First measurements indicate an operating power consumption of 330 mW @ 25MHz. This figure can be reduced, for typical applications, by 50 % by means of the built-in power controller.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11568/73776
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