Electrical simulation gives a good evaluation of the performances of Sigma-Delta modulators but could require too long simulation times. In this paper we introduce the use of Verilog-A, which provides the capability to model the circuit topology of Sigma-Delta modulators closely to the electrical level and achieving a considerable reduction of simulation time.
Sigma Delta ADC design using Verilog-A
FANUCCI, LUCA
2003-01-01
Abstract
Electrical simulation gives a good evaluation of the performances of Sigma-Delta modulators but could require too long simulation times. In this paper we introduce the use of Verilog-A, which provides the capability to model the circuit topology of Sigma-Delta modulators closely to the electrical level and achieving a considerable reduction of simulation time.File in questo prodotto:
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