A recent patent in the acoustics field introduced a new approach to quadraphonic data recording and playback. Based on fixed objective criteria, this method seems a promising technique to be used in high-fidelity systems where a characterization of the recording environment is needed. This may be useful for instance when documenting "sound events" such as music performances in real acoustic spaces or when composing virtual acoustic environments as for cinema sound tracks. A major bottleneck for real-time application of this system is represented by the physical implementation, which has to cope both with feasible implementation and no detriment to the high-end performances offered by the quadraphonic technique. This paper presents the architectural design issues for implementation of the quadraphonic recording algorithm: after the algorithm profiling, the hardware/software architecture is derived as a trade-off between complexity, performance and flexibility among different target technologies ranging from Digital Signal Processor (DSP) throughApplication Specific Instruction set Processor (ASIP) up to Field ProgrammableGate Arrays (FPGA) and Application Specific Integrated Circuit (ASIC). As a conclusion, preliminary implementation results for the most promising technology will be provided.
On the implementation of quadraphonic data recording
FANUCCI, LUCA;
2005-01-01
Abstract
A recent patent in the acoustics field introduced a new approach to quadraphonic data recording and playback. Based on fixed objective criteria, this method seems a promising technique to be used in high-fidelity systems where a characterization of the recording environment is needed. This may be useful for instance when documenting "sound events" such as music performances in real acoustic spaces or when composing virtual acoustic environments as for cinema sound tracks. A major bottleneck for real-time application of this system is represented by the physical implementation, which has to cope both with feasible implementation and no detriment to the high-end performances offered by the quadraphonic technique. This paper presents the architectural design issues for implementation of the quadraphonic recording algorithm: after the algorithm profiling, the hardware/software architecture is derived as a trade-off between complexity, performance and flexibility among different target technologies ranging from Digital Signal Processor (DSP) throughApplication Specific Instruction set Processor (ASIP) up to Field ProgrammableGate Arrays (FPGA) and Application Specific Integrated Circuit (ASIC). As a conclusion, preliminary implementation results for the most promising technology will be provided.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
